1. Field of the Invention
The present invention relates to a semiconductor memory device including a spare memory array to compensate for a failure of a normal memory array.
2. Description of the Background Art
FIG. 21 is a conceptional diagram illustrating a background-art semiconductor memory device including a spare memory array. A memory array of FIG. 21 consists of a normal memory array 1 and a spare memory array 2 used to replace the normal memory array 1 if the normal memory array 1 has some defective memory cell. Any normal memory cell in the normal memory array 1 is selected by an address signal. The address signal includes a column address signal and a row address signal. The column address signal is decoded by a normal column decoder 3 and a decoded signal is transmitted to a normal column selection line driving circuit 5. The normal column selection line driving circuit 5 activates one of a plurality of normal column selection lines 11 on the basis of the signal from the normal column decoder 3.
On the other hand, the row address signal is decoded by a normal row decoder 7 and a decoded signal is transmitted to a normal word line driving circuit 9. The normal word line driving circuit 9 activates one of a plurality of normal word lines 12 on the basis of the signal from the normal row decoder 7. FIG. 22 shows one of the normal column selection lines 11 and one of the normal word lines 12 being active in a normal operation. In FIG. 22, signal lines represented by heavy solid lines are active. A specific group of normal memory cells in the normal memory array 1 is selected by the active normal column selection line 11 and the active normal word line 12. Since a plurality of pairs of bit lines are provided with respect to one normal column selection line 11, a plurality of normal memory cells connected to the pairs of bit lines are selected at the same time.
FIG. 26 is a block diagram showing a relation between a selection signal line and pairs of bit lines. In FIG. 26 shown are a column selection line or a spare column selection line 40, sense amplifiers 41a to 41d to be enabled to operate by the column selection line 40, memory cells 42 to 44 which are arranged on separate columns and from which data are read out through one sense amplifier 41a, a pair of bit lines 45 connected to the sense amplifier 41a for reading and writing data from and into the memory cells 42 to 44 and the like, pairs of bit lines 46 to 48 connected to the sense amplifier 41b to 41d respectively, a normal word line 49 connected to the memory cell 42 and the like to select memory cells and spare word lines 50 and 51 connected to the spare memory cells 43 and 44 and the like respectively. When the column selection line 40 is activated, four pairs of bit lines are selected and eventually memory cells associated with an input address are selected.
If some normal memory cell is defective in the normal memory array 1, a normal word line or normal column selection line selecting the defective memory cell is replaced by a spare word line or spare column selection line in order to replace the normal memory cells in the normal memory array 1 by the spare memory cells in the spare memory array 2. For example, if some memory cell which is selected by a column selection line is defective, the column selection line is not activated thus not selecting the normal memory cells and instead a spare column selection line is activated to select the spare memory cells in the spare memory array 2 when the address associated with the defective memory cell is inputted.
For example, when a spare column selection line 13 is used to replace one of the normal column selection lines 11 including some defective memory cell, the normal row decoder 7 and the normal word line driving circuit 9 perform the same operation as in a case of no failure in response to a row address signal specifying a row having no defective memory cell. In this case, given a column address signal specifying one of the normal column selection lines 11 having the defective memory cell, a defective column address detecting circuit 4 detects the column address signal and disable the normal column decoder 3, and a spare column selection line driving circuit 6a outputs a signal to drive the spare column selection line 13. FIG. 23 shows the spare column selection line 13 and one of the normal word lines 12 being active. In FIG. 23, signal lines represented by heavy solid lines are active.
If required, another one of the normal column selection lines 11 is further replacement by, for example, a spare column selection line 14. Receiving a signal from the defective column address detecting circuit 4, a spare column selection line driving circuit 6b drives the spare column selection line 14.
Furthermore, there is a case where one of the normal word lines 12 having some defective memory cell should be replaced by a spare word line 15 or a spare word line 16. In this case, a defective row address detecting circuit 8 detects a row address signal specifying the defective normal memory cell. Detecting this row address signal, the defective row address detecting circuit 8 outputs a spare row selection signal to a spare word line driving circuit 10a or 10b to drive a spare word line 15 or 16 respectively and further outputs a normal row selection signal to disable the normal row decoder 7.
Referring next to FIG. 24, configuration and operation of the defective column address detecting circuit 4 will be discussed. FIG. 24 is a block diagram illustrating a configuration of column selection means. The column selection means refers to the defective column address detecting circuit 4, the normal column selection line driving circuit 5 and the spare column selection line driving circuits 6a and 6b in FIG. 21. A spare comparator 17 stores information regarding a defective column address and compares a column address signal CA with the stored information to detect whether or not the column address signal CA specifies the defective column address. Spare column selection signal generating means 18 generates a spare column selection signal to make a spare column selection line non-active if the spare comparator 17 judges that the defective column address is not specified. Receiving the spare column selection signal, the spare column selection line driving circuit 6 operates to make the spare column selection line non-active. Receiving the spare column selection signal from the spare column selection signal generating means 18, normal column selection signal generating means 19 generates a normal column selection signal to make normal column selection lines active. In response to the normal column selection signal, the normal column decoder 3 and the normal column selection line driving circuit 5 operate to activate only the column selection line associated with this address.
In contrast, the spare column selection signal generating means 18 generates a spare column selection signal to make the spare column selection line active if the spare comparator 17 judges that the defective column address is specified. Receiving the spare column selection signal, the spare column selection line driving circuit 6 operates to make the spare column selection line active. Receiving the spare column selection signal from the spare column selection signal generating means 18, the normal column selection signal generating means 19 generates the normal column selection signal to make the normal column selection lines non-active. In response to the normal column selection signal, the normal column decoder 3 and the normal column selection line driving circuit 5 makes the normal column selection line non-active.
FIG. 25 illustrates a circuit configuration of the normal column selection signal generating means 19 in the semiconductor memory device including a plurality of spare comparators 17 and two spare column selection lines. The normal column selection signal generating means 19 consists of a NAND gate 21 for outputting a negative AND (logical product) of spare column selection signals ZSCS1 and ZSCS2 outputted form spare column selection signal generating means 18a and 18b and an inverter 23c for inverting an output of the NAND gate 21.
The normal column decoder 3 includes a plurality of NAND gates 3a, 3b and the like. For example, each of the NAND gates 3a and 3b receives the address signal CA through a plurality of signal lines. Each of the NAND gates 3a, 3b and the like is enabled to output a signal of "L" when the address signal CA takes a value associated with the corresponding gate. FIG. 25 shows the NAND gates 3a and 3b each having a single input end for receiving the address signal CA, for simple illustration. If a normal column selection signal NCE is "H", one of the NAND gates 3a, 3b and the like which is enabled by the address signal CA outputs the signal of "L". If the normal column selection signal NCE is "L", none of the NAND gates 3a, 3b and the like constituting the normal column decoder 3 outputs the signal of "L".
If no replacement by the spare memory cells is made, the spare column selection signal generating means 18a and 18b generate the spare column selection signals ZSCS1 of "H" and ZSCS2 of "H", respectively. Receiving the spare column selection signals ZSCS1 and ZSCS2, the spare column selection line driving circuits 6a and 6b output signals SCSL1 and SCSL2 being non-active to make the spare column selection lines 13 and 14 non-active, respectively. Receiving the signals ZSCS1 and ZSCS2, the normal column selection signal generating means 19 outputs the normal column selection signal NCE of "H" for controlling the normal column decoder 3 to activate one of signals CSL1 to CSLn to be given the normal column selection lines 11.
Next, a replacement of a defective normal memory cell selected by one of the normal column selection lines 11 by a spare memory cell selected by the spare column selection line 13 will be discussed. When a column address associated with the defective normal memory cell is inputted, the spare column selection signal generating means 18a generates the spare column selection signal ZSCS1 of "L" on the basis of the judgment made by a spare comparator 17a. In response to the signal ZSCS1, the spare column selection line driving circuit 6a outputs the signal SCSL1 which is active to keep the spare column selection line 13 active in association with this address. Furthermore, the spare column selection signal ZSCS2 remains "H" for the spare column selection line 14 which is not used. Then, in response to the spare column selection signal ZSCS1 of "L", the normal column selection signal NCE comes into "L" and the normal column selection lines 11 become non-active in association with this address. Therefore, no memory cell in the memory cell array 1 having some defective memory cell is selected.
In the background-art semiconductor memory device having the above configuration, the normal column selection line or the normal word line which has been once replaced is never selected. Accordingly, a requirement of writing data into the replaced normal column or normal row to observe the effect of interference between memory cells in evaluation of the semiconductor memory device or failure analysis can not be satisfied.